The invention relates to the field of metal-oxide-semiconductor (MOS) configurations for MOS random access memories (RAMs) and, more particularly, to a memory cell configuration for static MOS RAMs.
Static MOS RAMs typically employ bistable, flip-flop circuits as memory cells for storing binary data. One particularly useful flip-flop circuit configured from four transistors and two resistor loads is frequently utilized in various memory cell structures because of its small size and low power requirements.
Conventionally, memory cells are fabricated with a single polycrystalline silicon (polysilicon) layer combined with an aluminum layer for forming transistors as well as interconnects in each memory cell. In particular, the aluminum layer is utilized for a power supply (Vcc) interconnect, a ground line (Vss) interconnect, and data line interconnects. While functioning adequately, the metal interconnects take up valuable space on a processed silicon wafer because all critical interconnect levels are in the same plane. This results in a smaller yield per wafer. The yield problem has been, in part, overcome by connecting the resistor loads to the bit lines which extend through the cell for accessing the cell, thereby eliminating the metal line for the Vcc connection and, thus, making the cell size smaller. More recently, the cell size has been further reduced by introducing a second polysilicon layer into the cell. The second polysilicon layer is used to form both the Vcc interconnect and the load resistors while an aluminum layer is used as a data line interconnect. An N+ diffusion silicon layer is used for the Vss interconnect.
Although the memory cell has diminished in size due to the layered levels, other yield problems are precipitated by the double polysilicon configuration. One problem area occurs from the second polysilicon layer intersecting with a buried contact region. Any such intersection with a buried contact region increases the defect density of the processed wafer.
The double polysilicon configuration creates a further yield problem because the additional layer of polysilicon requires creating an additional layer of silicon dioxide to isolate the polysilicon layer from whatever layer the polysilicon is adjacent to. This results in more process stages or steps. The increase of steps in the fabrication process has an inverse impact on the yield of the silicon wafer.